1. Field of the Invention
The invention provides a method of forming compliant electrical contacts that includes patterning a conductive layer into an array of compliant members, and then joining the array of compliant members to contact pads on a wafer.
2. Description of the Related Art
Electrical interconnections are often needed between integrated circuits, packages, boards, wafers, probes and other hardware which may be made from similar or dissimilar materials and may be coplanar or non-coplanar in nature. Often many connections are needed with semiconductor devices. Further, the features sizes and pitch of the connections to be interconnected are increased in number and reduced in size with advances of new generations of products over time. The characteristics that are desirable include the ability to have good electrical conduction while maintaining low electrical parasitics such as low inductance and capacitance for signal connections, provide good current carrying capability for power and ground connections, provide good mechanical integrity so electrical continuity can be assured even within or between different materials which may undergo expansion and contraction during power up, power down, thermal cycles, etc. This can produce stress and strains in the interconnection structures and thus lead to fatigue, opens, or electrical failures depending on the structure and application use conditions.
Chip interconnect reliability and processing requirements are dramatically changing with the industry-wide change from leaded solders to lead-free solder metallurgy. Moving to a lead-free interconnect technology typically induces reliability concerns due to limited data for specific application reliability and in some cases poor thermal cycling performance of non-leaded systems and structure, resulting in device failures. In some cases, solutions have addressed the reliability concerns using various approaches, however the interconnect resistance has increased, which is also undesirable. Current connections to wafers do not give sufficient compliance to movement.
The below-referenced U.S. patents disclose embodiments that were satisfactory for the purposes for which they were intended. The disclosures of the below-referenced prior U.S. patents, in their entireties, are hereby expressly incorporated by reference into the present invention for purposes including, but not limited to, indicating the background of the present invention and illustrating the state of the art. Further, the following U.S. patents explain many well known manufacturing processes/materials that can be used to form components mentioned below; however, the following U.S. patents do not disclose the unique methodology and/or structural features included within the invention, even if the inventive features utilize well known manufacturing processes/materials to achieve the unique methodology/structure. So as to not obscure the salient features of the invention, a detailed discussion of such well-known processing methods and materials is not included herein.
U.S. Pat. No. 6,528,349 shows monolithically fabricated compliant wafer level features fabricated on the wafer as additional steps of processing a wafer. These steps build a compliant interconnection up from the wafer utilizing photolithography, deposition processes (such as plating or sputter coating) to sequentially build a compliant interconnection off of a die pad, and forming solder for connection to a corresponding package for interconnection. When the compliant members are formed on the wafer, the processing and materials that can be used are limited so as not to damage the wafer or its internal circuitry.
Other references have shown the use of materials such as polymer materials to enhance the compliance of the interconnection (U.S. Pat. No. 6,690,081 and U.S. patent application Ser. No. 2003/0122229). Such references show compliant connections on a wafer at densities as high as 10000 to 20000 connections per centimeter squared. Again, however, while the monolithic fabrication of compliant members on a wafer can provide benefit by using semiconductor tools and sequential build up operations, this processing is limited to processes which do not damage the circuits and underlying interconnections.
These restrictions that result from forming the compliant members on the wafer limit the desired compliance of the build up connections. This can also negatively impact yields of useful and often expensive chips especially if the interconnection build up has defects which causes fall out or may degrade the performance or reliability of underlying devices and interconnection due to the multitude of additional processing steps being utilized. Other U.S. patents that are incorporated herein by reference including U.S. Pat. Nos. 5,023,205; 6,187,615; 5,736,448; 6,281,111 illustrate additional well known processing relating to compliant connections.